The present application generally relates to communication circuits and systems and more specifically to frequency synthesizers using a novel open-loop generation method. More particularly, the present application relates to frequency synthesizers capable of fast switching, frequency synthesizers capable of providing precise, high frequency clock references, and/or frequency synthesizers for use in communication equipment.
According to one particular application, radio frequency (RF) signal generation in mobile communication equipment, frequency synthesizers are utilized to provide a frequency source for a number of communication channels. In general, conventional frequency synthesizers have employed integer or fractional phase locked loops (PLLs) to generate a frequency signal. These conventional frequency synthesizers (PLL-based frequency synthesizers) utilize a phase locked loop comprised of a loop filter, a comparator circuit,. and a voltage controlled oscillator. These conventional PLL-based frequency synthesizers also have used dithering, and delta-sigma dithering methods to generate the fractional frequencies.
The oscillator has a control input coupled to the loop filter. The output of the comparator circuit is coupled to the loop filter. A first input of the comparator circuit is coupled to an integer divider and a delta-sigma averaging circuit. A second input of the comparator circuit is coupled to a reference signal. The combination of the integer divider and the delta-sigma averaging circuit constitute a fractional divider. The reference frequency signal can be generated from a crystal or other device. A delta-sigma fractional synthesizer is disclosed in U.S. Pat. No. 4,609,881 issued to Wells on Sep. 2, 1986.
Generally, such PLL-based frequency synthesizers are disadvantageous because they cannot be readily integrated on digital integrated circuits (ICs or chips). PLL-based frequency synthesizers require more expensive process technologies and are not compatible with the same CMOS technology that is used for base band and other digital control circuitry. As process technologies shrink in size, it becomes even more desirous to provide a radio architecture which is compatible with CMOS processes. U.S. Pat. Publication No. 2004/0066240 discusses certain advantages of migrating to digitally intensive synthesizer architectures.
In communication applications, the frequency synthesizer must often be capable of producing precise, high frequency clock references. Heretofore, most conventional synthesizers have utilized analog intensive designs to achieve precise, high frequency clock references. These conventional analog designs cannot take advantage of the digital processing capability inherent in advanced CMOS logic devices.
Therefore, there is a need for a frequency synthesizer that is more compatible with digital designs. Further still, there is a need for a synthesizer that does not utilize a conventional PLL-based design. Further still, there is a need to integrate frequency synthesizers into CMOS logic devices. Further still, there is a need for a frequency synthesizer capable of fast switching which does not have the traditional problems associated with analog-intensive designs. Yet further still, there is a need for a digital frequency synthesizer capable of producing precise high frequency clock signals.